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CDES'06: Proceedings

Last modified 2006-12-23 08:05

Author Index

Aboleaze, Mokhtar A.

Reducing Memory References for FFT Calculation

Ahuja, Narendra

Novel Complex Vauled Neural Networks

Al-Asaad, Hussain

Survey and Evaluation of Low-Power Flip-Flops

Al-Assadi, Waleed

Crosstalk at the Dynamic Node of Domino CMOS Circuits

Alghazo, Jaafar

Modeling and Realization of the Floating Point Inverse Square Root, Square Root, and Division unit (fP ISD) Using VHDL and FPGAs

Ali, Amin Ahsan

Realization of Digital Fuzzy Operations Using Multi-Valued Fredkin Gates

Arabnia, Hamid R.

A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs

Modified Carry Look Ahead BCD Adder With CMOS and Reversible Logic Implementation

A Reversible Programmable Logic Array (RPLA) Using Fredkin and Feynman Gates for Industrial Electronics and Applications

Novel NAND and AND Gate Using DNA Ligation and Two Transistors Implementations

Arul, Joseph

Improving the System Performance by a Dynamic File Prediction Model

Babu, Hafiz Md. Hasan

Realization of Digital Fuzzy Operations Using Multi-Valued Fredkin Gates

Bajpai, Rajnish

Novel NAND and AND Gate Using DNA Ligation and Two Transistors Implementations

Bhatia, Anshu

Simulation of a Turing Machine using EndoII Splicing Rules

Bhowmik, Anasua

Bandwidth-Friendly Cache Hierarchy

Botros, Nazeih

The Impact of Cache Organization in Optimizing Microprocessor Power Consumption

Camacho, Oscar

Zero Detect-Based Low Power Registers File Access

Chandorkar, Arun N.

Design of Low Power 4-Tap 8-Bit Adiabatic FIR Fillter

Chandra, T.S.

Simulation of a Turing Machine using EndoII Splicing Rules

Chandrasekhar, Pavankumar

Crosstalk at the Dynamic Node of Domino CMOS Circuits

Chen, I-Fan

Improving the System Performance by a Dynamic File Prediction Model

Chen, Yung-Yuan

Hybrid Error-Detection Approach with No Detection Latency for High-Performance Microprocessors

Chowdhury, Ahsan Raja

Realization of Digital Fuzzy Operations Using Multi-Valued Fredkin Gates

Chung, Chung-Ping

Instruction Fetch Energy Reduction Using Forward-Branch Bufferable Innermost Loop Buffer

Autonomous Instruction Memory Equipped with Dynamic Branch Handling Capability

Cui, Xiangdong

A New Processor Architecture with a New Program Driving Method

Deris, Safaai

Protein Secondary Structure Prediction Accuracy versus Reduction Methods

Dragffy, Gabriel

Bio-Inspired Celluar Systems With Cyclic Metamorphic Memory

Eisenbach, Markus

Teraflop Computing for Nanoscience

Elnaggar, Ayman I.

Reducing Memory References for FFT Calculation

Eshaghian-Wilner, Mary M.

Hierarchical Multi-Scale Architectures with Spin Waves

Graph Formations of Partial-Order Multiple-Sequence Alignments Using Nano and Micro-Scale Reconfigurable Meshes

Espinosa, Osvaldo

Zero Detect-Based Low Power Registers File Access

Farjah, Ebrahim

Bio-Inspired Celluar Systems With Cyclic Metamorphic Memory

Faulkner, J.S.

Teraflop Computing for Nanoscience

Franklin, Manoj

RHT: A Context-Based Return Address Predictor

Friesz, Aaron K.

Towards a Nanoscale Artificial Cortex

Ge, Jinming

Round-Robin Arbiter Design

Hannig, Frank

A Generic Framework for Rapid Prototyping of System-on-Chip Designs

Harsha, Prahladh

Communicating Distributed H systems with Simple Splicing Rules

Held, Werner

On the Management of Object Interrelationships

Hu, Erh-Wen

New DSP Benchmark based on Selectable Mode Vocoder (SMV)

Ilumoka, Abby

ANN-Based Spiral Inductor Parameter Extraction and Layout Re-Design

Jiang, Jingfei

A New Processor Architecture with a New Program Driving Method

Jiang, Lalin

A New Processor Architecture with a New Program Driving Method

Kahramanli, Sirzat

A Novel Essential Prime Implicant Identification Method for Exact Direct Cover Logic Minimization

Kandemir, Mahmut

Using Task Recomputation During Application Mapping in Parallel Embedded Architectures

Karapetyan, Vazgen

An Algorithm for Yield Improvement via Local Positioning and Resizing

Khalaf, Elias

Semi-Contiguous Memory Allocation for Efficient Sequential-Access

Khitun, Alex

Hierarchical Multi-Scale Architectures with Spin Waves

Kissler, Dmitrij

A Generic Framework for Rapid Prototyping of System-on-Chip Designs

Koc, Hakduran

Using Task Recomputation During Application Mapping in Parallel Embedded Architectures

Koch, Dirk

A Generic Framework for Rapid Prototyping of System-on-Chip Designs

Krithivasan, Kamala

Communicating Distributed H systems with Simple Splicing Rules

Kritihivasan, Kamala

Simulation of a Turing Machine using EndoII Splicing Rules

Ku, Cyril

New DSP Benchmark based on Selectable Mode Vocoder (SMV)

Kumar, Sandeep

A Configuration Concept for a Massively Parallel FPGA Architecture

Kupriyanov, Alexey

A Generic Framework for Rapid Prototyping of System-on-Chip Designs

Lau, Ling

Graph Formations of Partial-Order Multiple-Sequence Alignments Using Nano and Micro-Scale Reconfigurable Meshes

Leu, Kuen-Long

Hybrid Error-Detection Approach with No Detection Latency for High-Performance Microprocessors

Li, Xiaobo

A New Processor Architecture with a New Program Driving Method

Likharev, Konstantin K.

CMOL FPGA circuits

Lin, Li-Wen

Hybrid Error-Detection Approach with No Detection Latency for High-Performance Microprocessors

Luo, Ke

A New Processor Architecture with a New Program Driving Method

Ma, Chiyuan

A New Processor Architecture with a New Program Driving Method

Mangir, Tulin

Integrity and Integration Issues for Nano -Tube Based Interconnect Systems

Manwaring, Mark

An FPGA-based Experiment Platform for Hardware-Software Codesign and Hardware Emulation

Mohamed, Nagm

The Impact of Cache Organization in Optimizing Microprocessor Power Consumption

Murthy, Garimella Rama

Novel Complex Vauled Neural Networks

Nagaonkar, Yajuvendra

An FPGA-based Experiment Platform for Hardware-Software Codesign and Hardware Emulation

Navab, Shiva

Hierarchical Multi-Scale Architectures with Spin Waves

Graph Formations of Partial-Order Multiple-Sequence Alignments Using Nano and Micro-Scale Reconfigurable Meshes

Ni, Xiaoqiang

A New Processor Architecture with a New Program Driving Method

Nicholson, D.M.C.

Teraflop Computing for Nanoscience

Ospina G., Juan

A Computer Algebra Algorithm for the Symbolic Solution of a Problem involving the diffusion of adatoms on a Circular Wafer when sculpting a Nanopore with an Ion Beam

Paar, Christof

A Configuration Concept for a Massively Parallel FPGA Architecture

Pakdaman, Afshaneh

Towards a Nanoscale Artificial Cortex

Park, Yeonbum

ANN-Based Spiral Inductor Parameter Extraction and Layout Re-Design

Parker, Alice C.

Towards a Nanoscale Artificial Cortex

Pelzl, Jan

A Configuration Concept for a Massively Parallel FPGA Architecture

Pfeiffer, Gerd

A Configuration Concept for a Massively Parallel FPGA Architecture

Rameshwar, A.

Novel NAND and AND Gate Using DNA Ligation and Two Transistors Implementations

Rusanu, Aurelian

Teraflop Computing for Nanoscience

Russo, Andrew

New DSP Benchmark based on Selectable Mode Vocoder (SMV)

Samie, Mohammad

Bio-Inspired Celluar Systems With Cyclic Metamorphic Memory

Sayed, Ahmed

Survey and Evaluation of Low-Power Flip-Flops

Schimmler, Manfred

A Configuration Concept for a Massively Parallel FPGA Architecture

Sharma, Vipin

Crosstalk at the Dynamic Node of Domino CMOS Circuits

Shen, David

Graph Formations of Partial-Order Multiple-Sequence Alignments Using Nano and Micro-Scale Reconfigurable Meshes

Singh, Gurvinder

Design of Low Power 4-Tap 8-Bit Adiabatic FIR Fillter

Stocks, G.M.

Teraflop Computing for Nanoscience

Strukov, Dmitri B.

CMOL FPGA circuits

Su, Bogong

New DSP Benchmark based on Selectable Mode Vocoder (SMV)

Subair, Saad

Protein Secondary Structure Prediction Accuracy versus Reduction Methods

Talupur, Muralidhar

Communicating Distributed H systems with Simple Splicing Rules

Tamayo, Esteban García

A Computer Algebra Algorithm for the Symbolic Solution of a Problem involving the diffusion of adatoms on a Circular Wafer when sculpting a Nanopore with an Ion Beam

Teich, Juergen

A Generic Framework for Rapid Prototyping of System-on-Chip Designs

Tein, Bin-Hua

Instruction Fetch Energy Reduction Using Forward-Branch Bufferable Innermost Loop Buffer

Thapliyal, Himanshu

A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs

Modified Carry Look Ahead BCD Adder With CMOS and Reversible Logic Implementation

A Reversible Programmable Logic Array (RPLA) Using Fredkin and Feynman Gates for Industrial Electronics and Applications

Novel NAND and AND Gate Using DNA Ligation and Two Transistors Implementations

Tien, Kuo-Hsin

Improving the System Performance by a Dynamic File Prediction Model

Tosun, Suleyman

A Novel Essential Prime Implicant Identification Method for Exact Direct Cover Logic Minimization

Using Task Recomputation During Application Mapping in Parallel Embedded Architectures

Tucci, Ralph

Semi-Contiguous Memory Allocation for Efficient Sequential-Access

Uhl, Martin

On the Management of Object Interrelationships

Verma, Vishal

A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs

Villa, Luis

Zero Detect-Based Low Power Registers File Access

Wagner, Bryan W.

MolML: An Abstract Scripting Language for Assembly of Mechanical Nanocomputer Architectures

Wang, Jian

New DSP Benchmark based on Selectable Mode Vocoder (SMV)

Wang, Kang

Hierarchical Multi-Scale Architectures with Spin Waves

Wang, Yang

Teraflop Computing for Nanoscience

Way, Thomas P.

Compilation for Future Nanocomputer Architectures

MolML: An Abstract Scripting Language for Assembly of Mechanical Nanocomputer Architectures

Wu, I-Wei

Instruction Fetch Energy Reduction Using Forward-Branch Bufferable Innermost Loop Buffer

Wu, Jia-Shian

Improving the System Performance by a Dynamic File Prediction Model

Yang, Hui-Chin

Autonomous Instruction Memory Equipped with Dynamic Branch Handling Capability

Yeh, Tsozen

Improving the System Performance by a Dynamic File Prediction Model

Zahran, Mohamed

RHT: A Context-Based Return Address Predictor

Bandwidth-Friendly Cache Hierarchy

Zarate, Moises

Zero Detect-Based Low Power Registers File Access

Zhang, Wei

The Impact of Cache Organization in Optimizing Microprocessor Power Consumption

Zhou, Huiping

A New Processor Architecture with a New Program Driving Method

Zhou, Zhou

A New Processor Architecture with a New Program Driving Method

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CDES'06: Proceedings