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The 2006 World Congress in Computer Science
Computer Engineering, and Applied Computing

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You are here: Home → WORLDCOMP'06 Publications → ERSA'06 → ERSA'06: Proceedings

ERSA'06 Proceedings

Foreword

Table of Contents

Author Index

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ERSA'06: Proceedings

Last modified 2006-11-19 18:15

Author Index

Aggarwal, Vikas

Compile- and Run-Time Services for Distributed Hetergeneous Reconfigurable Computing

Agosta, Giovanni

Synthesis of Object Oriented Models on Reconfigurable Hardware

Agron, Jason

The Case for High Level Programming Models for Reconfigurable Computers

Amano, Hideharu

A Parametric Study of Scalable Interconnects on FPGAs

Amicucci, Carlo

SyCERS: a SystemC Design Exploration Framework for SoC Reconfigurable Architecture

Anderson, Erik

The Case for High Level Programming Models for Reconfigurable Computers

Andrews, David

The Case for High Level Programming Models for Reconfigurable Computers

Avasare, Prabhat

Exploiting Hierarchical Configuration to Improve Run-Time MPSoC Task Assignment

Baijot, Fabrice

The Case for High Level Programming Models for Reconfigurable Computers

Barfield, Gabe

Compile- and Run-Time Services for Distributed Hetergeneous Reconfigurable Computing

Bi, Yu

Hardware Acceleration of Parallel Lagged-Fibonacci Pseudo Random Number Generation

Bruschi, Francesco

Synthesis of Object Oriented Models on Reconfigurable Hardware

Chan, Herwin

Process Isolation for Reconfigurable Hardware

Chandy, John

A Generic Lookup Cache Architecture for Network Processing Applications

Corporaal, Henk

Exploiting Hierarchical Configuration to Improve Run-Time MPSoC Task Assignment

Delgado-Frias, J.

Mapping and Performance of DSP Benchmarks on a Medium-Grain Reconfigurable Architecture

DeMara, Ronald

Complexity and Performance Evaluation of Two Partial Reconfiguration Interfaces on FPGAs: A Case Study

Diguet, Jean-Philippe

RTOS-Based Hardware Software Communications and Configuration Management in the Context of a Smart Camera

Dragffy, Gabriel

Metamorphic Memory Based Bio-Inspired Reconfigurable Celluar Systems

Ejnioui, Abdel

Complexity and Performance Evaluation of Two Partial Reconfiguration Interfaces on FPGAs: A Case Study

El Khodary, Milad

RTOS-Based Hardware Software Communications and Configuration Management in the Context of a Smart Camera

Erdogan, Ahmet T.

Low Power Programmable FIR Filtering IP Cores Targeting System-on-a-Reprogrammable-Chip (SoRC)

Eustache, Yvan

RTOS-Based Hardware Software Communications and Configuration Management in the Context of a Smart Camera

Fan, Jenny

A Dual Configuration BIST-Based Modular Diagnostic Methodology for Embedded Cores in FPGAs

Farjah, Ebrahim

Metamorphic Memory Based Bio-Inspired Reconfigurable Celluar Systems

Ferrandi, Fabrizio

SyCERS: a SystemC Design Exploration Framework for SoC Reconfigurable Architecture

George, Alan

Compile- and Run-Time Services for Distributed Hetergeneous Reconfigurable Computing

Glabb, Ryan

Multi-Mode Operator for SHA-2 Hash Functions

Gokhale, Maya

Promises and Pitfalls of Reconfigurable Supercomputing

Greco, James

Compile- and Run-Time Services for Distributed Hetergeneous Reconfigurable Computing

Guo, Yuanqing

A Column Arrangement Algorithm for a Coarse-grained Reconfigurable Architecture

Hameed, Abdul

Low Power Programmable FIR Filtering IP Cores Targeting System-on-a-Reprogrammable-Chip (SoRC)

Harrison, Robert

Hardware Acceleration of Parallel Lagged-Fibonacci Pseudo Random Number Generation

He, Chuan

Group-Alignment based Accurate Floating-Point Summation on FPGAs

Heysters, Paul

Hydra: An Energy-efficient and Reconfigurable Network Interface

The Era of Reconfigurable Computing

Coarse-Grained Reconfigurable Computing for Power Aware Applications

Heysters, Paul M.

Reconfigurable Turbo/Viterbi Channel Decoder in the Coarse-Grained Montium Architecture

Ho, Chun Hok

Reconfigurable Acceleration of Robust Frequency-Domain Echo Cancellation

Hoede, Cornelis

A Column Arrangement Algorithm for a Coarse-grained Reconfigurable Architecture

Holland, Brian

Compile- and Run-Time Services for Distributed Hetergeneous Reconfigurable Computing

Hsu, Chung

Promises and Pitfalls of Reconfigurable Supercomputing

Huang, Xinming

An FPGA based Co-Design Architecture for MIMO Lattice Decoders

Huo, Jiaquan

Reconfigurable Acceleration of Robust Frequency-Domain Echo Cancellation

Imbert, Laurent

Multi-Mode Operator for SHA-2 Hash Functions

Javelo, Adrian

Floating-Point Unit Reuse in an FPGA Implementation of a Ray-Triangle Intersection Algorithm

Jean, Jack

Architectural Support for Runtime 2D Partial Reconfiguration

Jullien, Graham

Multi-Mode Operator for SHA-2 Hash Functions

Jung, Hong-Jip

Efficient FPGA-based Implementations of the MIMO-OFDM Physical Layer

Kalte, Heiko

Relocation and Defragmentation for Heterogeneous Reconfigurable Systems

Kearney, David

A High Speed, Run Time Reconfigurable Image Acquisition processor for a Missile Approach Warning System

An Area Time Efficient Field Programmable Mersenne Twister Uniform Random Number Generator

Khan, Muhammad Akhtar

Low Power Programmable FIR Filtering IP Cores Targeting System-on-a-Reprogrammable-Chip (SoRC)

Kindratenko, Volodymyr

Code Partitioning for Reconfigurable High-Performance Computing: A Case Study

Kobayashi, Fuminori

Differential Reconfiguration Architecture suitable for a Holographic Memory

Logic Synthesis and Place-and-Route Environment for ORGAs

Shield Effect Analysis for a Gate Array on An Optically Reconfigurable Gate Array

Koch, Dirk

Searching RC5-Keys with Distributed Reconfigurable Computing

Koerber, Matthiaas

Searching RC5-Keys with Distributed Reconfigurable Computing

Koester, Markus

Relocation and Defragmentation for Heterogeneous Reconfigurable Systems

Koibuchi, Michihiro

A Parametric Study of Scalable Interconnects on FPGAs

Komp, Ed

The Case for High Level Programming Models for Reconfigurable Computers

Kong, Seong

Intrinsic Embedded Hardware Evolution of Block-based Neural Networks

Lange, Sebastian

Cache Architectures for Reconfigurable Hardware

Larson, Jonathan

Mapping and Performance of DSP Benchmarks on a Medium-Grain Reconfigurable Architecture

Leeser, Miriam

Efficient Use of Communications Between an FPGAs Embedded Processor and its Reconfigurable Logic

Liang, Cao

An FPGA based Co-Design Architecture for MIMO Lattice Decoders

Liang, Xuejun

Combinatorial Optimization in Mapping Generalized Template Matching onto Reconfigurable Computers

Lu, Mi

Group-Alignment based Accurate Floating-Point Summation on FPGAs

Luk, Wayne

Reconfigurable Acceleration of Robust Frequency-Domain Echo Cancellation

Ma, Jing

An FPGA based Co-Design Architecture for MIMO Lattice Decoders

Malluhi, Qutaibah

Combinatorial Optimization in Mapping Generalized Template Matching onto Reconfigurable Computers

Matsutani, Hiroki

A Parametric Study of Scalable Interconnects on FPGAs

Mehdipour, Farhad

GifT:A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs

Memik, Seda

A Sensor Distribution Algorithm for FPGAs with Minimal Dynamic Reconfiguration Overhead

Merchant, Saumil

Intrinsic Embedded Hardware Evolution of Block-based Neural Networks

Middendorf, Martin

Cache Architectures for Reconfigurable Hardware

Miyano, Mototsugu

Differential Reconfiguration Architecture suitable for a Holographic Memory

Mondal, Somsubhra

A Sensor Distribution Algorithm for FPGAs with Minimal Dynamic Reconfiguration Overhead

Mukherjee, Rajarshi

A Sensor Distribution Algorithm for FPGAs with Minimal Dynamic Reconfiguration Overhead

Murakami, Kazuaki

GifT:A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs

Myjak, Mitchell

Mapping and Performance of DSP Benchmarks on a Medium-Grain Reconfigurable Architecture

Nollet, Vincent

Exploiting Hierarchical Configuration to Improve Run-Time MPSoC Task Assignment

Noori, Hamid

GifT:A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs

Nordholm, Sven

Reconfigurable Acceleration of Robust Frequency-Domain Echo Cancellation

Noseworthy, Joshua

Efficient Use of Communications Between an FPGAs Embedded Processor and its Reconfigurable Logic

Park, Jeoong Sung

Efficient FPGA-based Implementations of the MIMO-OFDM Physical Layer

Peck, Wesley

The Case for High Level Programming Models for Reconfigurable Computers

Peterson, Gregory

Intrinsic Embedded Hardware Evolution of Block-based Neural Networks

Hardware Acceleration of Parallel Lagged-Fibonacci Pseudo Random Number Generation

Porrmann, Mario

Relocation and Defragmentation for Heterogeneous Reconfigurable Systems

Prasanna, Viktor

Efficient FPGA-based Implementations of the MIMO-OFDM Physical Layer

Qin, Guan

Group-Alignment based Accurate Floating-Point Summation on FPGAs

Rauwerda, Gerard

Hydra: An Energy-efficient and Reconfigurable Network Interface

Rauwerda, Gerard K.

Reconfigurable Turbo/Viterbi Channel Decoder in the Coarse-Grained Montium Architecture

Rickett, Christopher

Promises and Pitfalls of Reconfigurable Supercomputing

Rowen, Chris

The Reinvention of the Microprocessor

Using configurable processors for high-efficiency multiple-processor systems

Saheb Zamani, Morteza

GifT:A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs

Samie, Mohammad

Metamorphic Memory Based Bio-Inspired Reconfigurable Celluar Systems

Santambrogio, Marco

SyCERS: a SystemC Design Exploration Framework for SoC Reconfigurable Architecture

Synthesis of Object Oriented Models on Reconfigurable Hardware

Sarvi, Alireza

A Dual Configuration BIST-Based Modular Diagnostic Methodology for Embedded Cores in FPGAs

Sass, Ron

The Case for High Level Programming Models for Reconfigurable Computers

Sattler, Jason

Complexity and Performance Evaluation of Two Partial Reconfiguration Interfaces on FPGAs: A Case Study

Schaumont, Patrick

Process Isolation for Reconfigurable Hardware

Sciuto, Donatella

SyCERS: a SystemC Design Exploration Framework for SoC Reconfigurable Architecture

Synthesis of Object Oriented Models on Reconfigurable Hardware

Scrofano, Ronald

Promises and Pitfalls of Reconfigurable Supercomputing

Sedighi, Mehdi

GifT:A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs

Singaraju, Janardhan

A Generic Lookup Cache Architecture for Network Processing Applications

Smit, Gerard

A Column Arrangement Algorithm for a Coarse-grained Reconfigurable Architecture

Hydra: An Energy-efficient and Reconfigurable Network Interface

Smit, Gerard J.M.

Reconfigurable Turbo/Viterbi Channel Decoder in the Coarse-Grained Montium Architecture

Smith, Steven

Dynamic Scheduling and Resource Management in Heterogeneous Computing Environments with Reconfigurable Hardware

Sriram, Vinay

A High Speed, Run Time Reconfigurable Image Acquisition processor for a Missile Approach Warning System

An Area Time Efficient Field Programmable Mersenne Twister Uniform Random Number Generator

Stamm, Reto

A Dual Configuration BIST-Based Modular Diagnostic Methodology for Embedded Cores in FPGAs

Stevens, Jim

The Case for High Level Programming Models for Reconfigurable Computers

Tan, Heng

Complexity and Performance Evaluation of Two Partial Reconfiguration Interfaces on FPGAs: A Case Study

Teich, Juergen

Searching RC5-Keys with Distributed Reconfigurable Computing

Thakkar, Anuja

Complexity and Performance Evaluation of Two Partial Reconfiguration Interfaces on FPGAs: A Case Study

Tisseraud, Arnaud

Multi-Mode Operator for SHA-2 Hash Functions

Tripp, Justin

Promises and Pitfalls of Reconfigurable Supercomputing

Troxel, Ian

Compile- and Run-Time Services for Distributed Hetergeneous Reconfigurable Computing

Ulmer, Craig

Floating-Point Unit Reuse in an FPGA Implementation of a Ray-Triangle Intersection Algorithm

van Benthem, Casper R.W.

Reconfigurable Turbo/Viterbi Channel Decoder in the Coarse-Grained Montium Architecture

van de Burgwal, Marcel

Hydra: An Energy-efficient and Reconfigurable Network Interface

Verbauwhede, Ingrid

Process Isolation for Reconfigurable Hardware

Verkest, Diederik

Exploiting Hierarchical Configuration to Improve Run-Time MPSoC Task Assignment

Veyrat-Charvillon, Nicolas

Multi-Mode Operator for SHA-2 Hash Functions

Wang, Daihan

A Parametric Study of Scalable Interconnects on FPGAs

Wang, Fei

Architectural Support for Runtime 2D Partial Reconfiguration

Warren, Lee

Hardware Acceleration of Parallel Lagged-Fibonacci Pseudo Random Number Generation

Watanabe, Minoru

Differential Reconfiguration Architecture suitable for a Holographic Memory

Logic Synthesis and Place-and-Route Environment for ORGAs

Shield Effect Analysis for a Gate Array on An Optically Reconfigurable Gate Array

Yiu, Ka Fai Cedric

Reconfigurable Acceleration of Robust Frequency-Domain Echo Cancellation

Yoshimi, Masato

A Parametric Study of Scalable Interconnects on FPGAs

Zhao, Wei

Group-Alignment based Accurate Floating-Point Summation on FPGAs

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