General Keynote - Prof. David A. Patterson
The Parallel Computing Landscape: A Berkeley View 2.0
Professor David A. Patterson
University of California at Berkeley, California, USA
Member, National Academy of Engineering
Member, National Academy of Sciences
Fellow of IEEE, ACM, and AAAS
Shared (with John Hennessy) the IEEE John von Neumann Medal
Date: July 14, 2008
Location: Lance Burton Theater
In December 2006 we published a broad survey of the issues for
the whole field concerning the multicore/manycore sea change (see
view.eecs.berkeley.edu). We view the ultimate goal as being able to
productively create efficient and correct software that smoothly scales
when the number of cores per chip doubles biennially. This talk covers
the specific research agenda that a large group of us at Berkeley are
going to follow (see parlab.eecs.berkeley.edu).
To take a fresh approach to the longstanding parallel computing problem, our research agenda will be driven by compelling applications developed by domain experts. Historically, past efforts to resolve these challenges have often been driven "bottom-up" from the hardware, with applications an afterthought. We will focus on exciting new applications that need much more computing horsepower to run well rather than on legacy programs that already run well on today's computers. Our applications are in the areas of personal health, image retrieval, music, speech understanding, and browsers.
The development of parallel software is the heart of the research agenda. The task will be divided into two layers: an efficiency layer that aims at low overhead for 10 percent of the best programmers, and a productivity layer for the rest of the programming community--including domain experts--that reuses the parallel software developed at the efficiency layer. Key to this approach is a layer of libraries and programming frameworks centered around the 13 computational bottlenecks ("dwarfs") that we identified in the Berkeley View report. We will also create a Composition and Coordination Language to make it easier to compose these components. Finally, we will rely on autotuning to map the software efficiently to a particular parallel computer. Past attempts have often relied on a single programming abstraction and language for everyone and on parallelizing compilers.
The role of the operating systems and the architecture in this project is to support software and applications in achieving the ultimate goal, rather than the conventional approach of fixing the environment in which parallel software must survive. Examples include primitives like thin hypervisors and libraries for the operating system and hardware support for partitioning and fast barrier synchronization.
We will prototype the hardware of the future using field programmable gate arrays (FPGAs), which we believe are fast enough to be interesting to parallel software researchers yet flexible enough to "tape out" new designs every day while being cheap enough that university researchers can afford to construct systems containing hundreds of processors. This prototyping infrastructure is called RAMP (Research Accelerator for Multiple Processors), which is being developed by a consortium of universities and companies (see ramp.eecs.berkeley.edu).