CDES'09: July 16, 2009 Schedule

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6:45am - 5:00pm:  REGISTRATION (Second Floor, Conference Lobby: 1-5)


SESSION 4-CDES:   ALGORITHMS, LOGIC, CIRCUIT/HARDWARE DESIGN, & TOOLS
                  Chairs: Prof. Scott C. Smith* & Prof. Hussain Al-Asaad**
                  *University of Arkansas, Fayetteville, Arkansas, USA
                  **University of California, Davis, California, USA
                  July 16, 2009 (Thursday); 08:00am - 01:20pm
                  (LOCATION: Titanium Room)

08:00 - 08:20am:  Delay-Insensitive Ternary Logic
                  Ravi Sankar Parameswaran Nair, Scott C. Smith, and Jia Di
                  University of Arkansas, USA

08:20 - 08:40am:  Null Conventional Logic (NCL) Implementation of a Bit-Wise Pipeline
                  Dual-Rail (NCL) 2^s Complement Multiplier
                  Indira P. Dugganapally, Waleed K. Al-Assadi
                  Missouri University of Science and Technology, Rolla, Missouri, USA

08:40 - 09:00am:  Moving from Binary towards Multi-valued logic
                  Vasundara Patel K S and K S Gurumurthy
                  BMSCE and UVCE

09:00 - 09:20am:  A 5T SRAM Cell with 4 Power Terminals for Read/Write/Standby Assist
                  Richard F. Hobson
                  Simon Fraser University, Canada

09:20 - 09:40am:  Performance Evaluation Model of Branch Input Vectors using Neural Network
                  Jong Wook Kwak and Ju-Hwan Kim
                  Yeungnam University, Republic of Korea &
                  Seoul National University, Republic of Korea

09:40 - 10:00am:  Compact Design of a Combined MixColumn/InvMixColumn Transformation Module
                  for AES
                  Yong-Sung Jeon and Jong-Wook Han
                  Electronics and Telecommunications Research Institude, Korea

10:00 - 10:20am:  Detection and Isolation of Faulty Processors in Multiprocessor Systems
                  via TMR-Based Time Redundant Task Scheduling
                  Hussain Al-Asaad
                  University of California, Davis, California, USA

10:20 - 10:40am:  BREAK

10:40 - 11:00am:  Reducing the Far-end Crosstalk Using Advanced Guard Trace in PCB
                  Transmission Lines
                  Sung-Bin Kim, Se-Jin Ko, Ki-Young Kim, Seok-Yoon Kim
                  Soongsil University, Republic of Korea

11:00 - 11:20am:  Analytic Models for Peak Current Computation in General Interconnect Circuits
                  Ki-Young Kim, Sung-Bin Kim, Se-Zin Ko, Seok-Yoon Kim
                  Soongsil University, Republic of Korea

11:20 - 11:40am:  The Computing Technology and John von Neumann's Computer Architecture
                  Giving Way to Optical Computing
                  Mushtaq Ahmad
                  FCSE, GIK Institute of Engineering & Technology, Pakistan

11:40 - 12:00pm:  Kernel Level Secure Synchronous (KSS) IPC Design
                  Pramila Chawan, Pravin K. Malviya, Rajeshkumar R. Chavan
                  V.J.T.I. Mumbai, India

12:00 - 12:20pm:  CLIW - Clue - Compressed Long Instruction Words: The Future for all
                  New Instruction Set Designs
                  Brett Davis
                  Activision-Blizzard Inc., USA

12:20 - 12:40pm:  A Reconfigurable Superscalar Processor Architecture for FPGA-Based Designs
                  Jorge Ortiz
                  University of Kansas, Lawrence, Kansas, USA

12:40 - 01:00pm:  Exploring an AES Crypto-Processor Design Using a Asynchronous Toolset:
                  A Case Study
                  Akbar Jafarzadef, A. Movaghar, Behnam Ghavami
                  AUT & Sharif University, Iran

01:00 - 01:20pm:  EM-Modeling of Excitation Source in Transverse Wave Approach (TWA) for
                  RF Integrated Circuits Applications
                  M. Ayari, T. Aguili, H. Temimi, H. Baudrand
                  SysCom Laboratory, National Engineering School, Tunisia &
                  Virginia Polytechnic Institute and State University, USA &
                  ENSEEHIT - Polytechnic National Institute, Toulouse, France

01:20 - 02:00pm:  LUNCH (On Your Own)

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