CDES'10: July 15, 2010 Schedule

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6:45am - 4:00pm:  REGISTRATION (Second Floor, Conference Lobby: 1-5)


SESSION 6-CDES:   POWER ANALYSIS AND ENERGY + FPGA + NOVEL APPLICATIONS/ALGORITHMS + TOOLS
                  Chair: Sunil Kr. Singh, Uttarakhand Technilcal University, Dehradun, India
                  July 15, 2010 (Thursday); 09:20am - 12:40pm
                  (LOCATION: Chapel)

09:20 - 09:40am:  A Low-Power, Pulsed Domino CMOS 64-bit Adder
                  Richard F. Hobson
                  Simon Fraser University, Burnaby, B.C., Canada

09:40 - 10:00am:  Leakage Power Analysis of Multi-bit Adders Using Transistor
                  Gate Length Increase
                  Savithra Eratne, Claudia Romo, Eugene John
                  University of Texas at San Antonio, Texas, USA

10:00 - 10:20am:  An O(n) Parallel Shortest Path Algorithm and Its Hardware Implementation
                  Jaehwan John Lee and Xiang Xiao
                  Indiana University-Purdue University Indianapolis, Indiana, USA

10:20 - 10:40am:  BREAK

10:40 - 11:00am:  ISLEEN AID - An Alternative Input Method for Visually Impaired People
                  R. Kevin, R. Balaji, N. Nityanandam
                  Anna University, India

----------->      Note: We anticipate a number of speaker no-shows for the following
                  talks (due to potential delay in obtaining US visa, non registration,
                  ...). In cases of no-shows, the presentations can be moved up to
                  close time gaps in the session.

11:00 - 11:20am:  Improved Energy Monitoring and Prognostics of Servers via
                  High-Accuracy  Real-Time Synchronization of Internal Telemetry Signals
                  Kenny C. Gross and Kalyan Vaidyanathan
                  Oracle Corp., USA

11:20 - 11:40am:  Dynamic Power Reduction in a Novel CMOS 5T-SRAM for Low-Power SoC
                  Hooman Jarollahi and Richard F. Hobson
                  Simon Fraser University, B.C., Canada

11:40 - 12:00pm:  Quantum-Dot Cellular Automata Implementation of FPGA Configurable
                  Logic Blocks
                  Mohammed Niamat, Tejas Raviraj, Sowmya Panuganti, Srinivas Vemuru
                  University of Toledo, Ohio, USA;
                  Ohio Northern University, Ohio, USA

12:00 - 12:20pm:  Development of FPGA Chip for Laser-based Distance Measurer for
                  Defense Applications
                  Paramjit Kaur, Opinder Sharma, Gautham Thyagarajan
                  Wayne State University, Detroit, Michigan, USA

12:20 - 12:40pm:  Extension of Superblock Technique to Hyperblock Using Predicate
                  Hierarchy Graph
                  Sweta Verma, Ranjit Biswas, J. B. Singh
                  Shobhit University, Meerut

12:40 - 01:40pm:  LUNCH (On Your Own)


01:40 - 06:00pm:  During this period, CDES'10 attendees are encouraged to participate
                  in sessions belonging to PDPTA'10, ERSA'10, ESA'10, ICWN'10,
                  MSV'10, SAM'10, and FECS'10. These sessions discuss topics that
                  significantly overlap the scope of CDES'10.

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