CDES'12: Tuesday, July 17, 2012 Schedule

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6:45am - 5:00pm:  REGISTRATION (Second Floor, Conference Lobby: 1-5)


08:00a - 12:40p:  During this period, CDES attendees are encouraged to participate
                  in sessions belonging to ESA'12, FECS'12, ICWN'12, or PDPTA'12.
                  These sessions discuss topics that significantly overlap the
                  scope of CDES'12.


SESSION 3-CDES:   HPC + DESIGN ISSUES + FPGA + GPU + NOC + EMBEDDED SYSTEMS +
                  ALGORITHMS, LOGIC, CIRCUIT/HARDWARE DESIGN, AND TOOLS
                  Co-Chairs: Dr. Scott C. Smith, Director of the Asynchronous Digital Design Lab.,
                             University of Arkansas, Fayetteville, Arkansas, USA;
                             Dr. Askar Boranbayev, Nazarbayev University, Kazakhstan.
                  July 17, 2012 (Tuesday); 12:40pm - 03:20pm
                  (LOCATION: Ballroom 7)

12:40 - 01:00pm:  SD-MARC: A New Multi-Processor Architecture
                  Somdip Dey
                  University of Calcutta, India

01:00 - 01:20pm:  A New Technique To Use A Parallel Compiler for Multi-core
                  Microcontrollers
                  Somdip Dey
                  University of Calcutta, India

01:20 - 01:40pm:  Datacenter Design and Implementation at the University
                  Askar Boranbayev and Sergey Belov
                  Nazarbayev University, Kazakhstan

01:40 - 02:00pm:  Area-Time Efficient Digit-Serial-Serial Two's Complement Multiplier
                  Essam Elsayed and Hatem M. El-Boghdadi
                  Faculty of Engineering, Cairo University, Giza, Egypt

02:00 - 02:20pm:  Analysis of Notebook Computer Chassis Design for Hard Disk Drive
                  and Speaker Mounting
                  J. Q. Mou, Fukun Lai, I. B. L. See, and W. Z. Lin
                  Data Storage Institute, Singapore

02:20 - 02:40pm:  High Fidelity Telemetry Signal Synthesis for Improved Electronic
                  Prognostics
                  Ram C. Dhanekula and Kenny C. Gross
                  Oracle Corporation, San Diego, California, USA

02:40 - 03:00pm:  Accurate Throughput Derivation of Pipelined NULL Convention Logic
                  Asynchronous Circuits
                  Liang Zhou and Scott C. Smith
                  University of Arkansas, Arkansas, USA

03:00 - 03:20pm:  Effect of Channel Lengthening and Threshold Voltage Variation on a
                  Nanometric Gate's Delay and Power
                  Azam Beg and Amr Elchouemi
                  United Arab Emirates University, UAE;
                  Hewlett Packard, Austin, Texas, USA


03:30 - 05:30pm:  During this period, CDES attendees are encouraged to participate
                  in sessions belonging to ESA'12, FECS'12, ICWN'12, or PDPTA'12.
                  These sessions discuss topics that significantly overlap the
                  scope of CDES'12.


05:30 - 06:30pm:  POSTER SESSION A-ESA-CDES
                  July 17, 2012 (Tuesday)
                  (LOCATION: Hallways of Ballrooms 1-5)

                  O. Modeling and Development of a Large Application on RTOS
                     Sang Cheol Kim, Young-Jin Choi, Seon-Tae Kim
                     Electronics and Telecommunications Research Institute (ETRI), Daejeon,
                     South Korea;  University of Science and Technology (UST), Daejeon,
                     South Korea
                  O. Synchronization of a Complex Dynamical Network With Nonidentical Nodes
                     via Dynamic Feedback Control
                     T. H. Lee, J. H. Park, H. Y. Jung, S. M. Lee
                     Yeungnam University;  Daegu University, Republic of Korea
                  O. More posters will be added at a later time.


06:00 - 09:00pm:  TUTORIALS + INVITED PRESENTATIONS
                  (Please see the lists at the begining of this booklet)

To select a different schedule CLICK HERE